The reliability and performance of high performance circuit packages can be enhanced by matching the coefficient of thermal expansion (CTE) of the base carrier (circuit board, chip carrier, etc.) to the components to be mounted.
The primary drivers for this are large solder ball grid array (BGA) interconnects, and other soldered interfaces. As chip I/O increases beyond the capability of peripheral lead devices, area array interconnects such as the BGA are the preferred method for making large numbers of connections between chip carriers and cards/boards. If the CTE of the chip carrier does not match the card, as is the case with an epoxy-glass card and ceramic chip carrier, then the size of the BGA will be limited due to strain-induced fatigue of the solder joints during thermal cycling.
As module size increases beyond fatigue limits for solder ball attach, current practice dictates the use of a separate connector system to relieve the CTE mismatch between the two packages. Typical connectors include flex cables or sockets. This hardware adds cost and limits performance due to increased noise and power distribution inductance. If the package CTEs are matched by restraining the expansion of the card/board, then very large chip carriers can be reliably assembled directly to a circuit board using soldered BGA. This provides the large number of interconnects required for high performance single-chip and multi-chip carriers and eliminates the cost and performance penalty of a connector system.
When a large number of chip carriers or chips are assembled to a card/board, the average power and instantaneous current demand become quite high. It is desirable under these circumstances to separate the signal and power distribution function within the card/board so that each can be optimized to its particular function. To accomplish this, a separate laminated power structure (LPS) can be fabricated using very thick copper planes and attached to a card or board optimized for signal interconnects. Power is transferred from the LPS to the card or board through a large number of vias which pass from the LPS, through the card, to the BGA's on the card or board surface. It is further desirable to eliminate any intermediate connector system between the LPS and card/module. This reduces the overall inductance of the power distribution system and allows for higher simultaneous driver switching and/or faster drivers. A soldered or metallurgical interconnection provides the lowest inductance interface, and eliminates the cost of an LPS to card/module connector.
If the card/board is CTE controlled, or of a material set yielding a CTE different from the LPS, then the LPS must be CTE matched to the card to allow this direct soldered attachment. In this way, the need for CTE matching propagates through the package to all levels involved in large area soldered interconnects, and can in fact begin at the chip carrier if the chip assembly technique requires a CTE match between the chip and the chip carrier. So in the full implication, CTE control or matching can be used in the chip carrier, the card and the LPS or in any combination.
Current practice for CTE control in laminate structures involves replacing copper power layers with copper clad Invar (CIC) or other low expansion metals. The Invar alloy used in this cladding has near zero CTE and will compensate/reduce the CTE of the overall laminate structure. The amount of CTE reduction will depend on the ratio of Invar to copper in the overall structure, and the compliance and CTE of the insulation layers used in the laminate.
Due to the presence of iron alloy, Invar (and CIC) is difficult to machine even in thin layers, and requires special techniques to enable the mechanical drilling of power vias. In an LPS application, heavy power planes with low resistivity are required. 10-100 oz. of copper might be required in a typical LPS. Significantly more material would be needed if CIC were used as the power plane material. This is because at equivalent thickness, the copper content would be reduced; and compared to copper, Invar is a poor conductor. The large thickness of Invar in this type of structure makes mechanical drilling of the power vias impractical.
One technique for forming the expansion controlled card or carrier is to utilize alternating layers of dielectric material, copper, and very thin layers of an electrically conducting, expansion stabilizing material such as a laminate of copper/Invar.RTM./copper ("CIC"). One type of high performance insulating material is silica filled polytetrafluoroethylene (PTFE), with the carrier being formed of alternating laminae of CIC, copper, and filled PTFE. Similar types of carriers can be formed using polyimides or glass filled epoxy known as FR4 as the dielectric material.
The structures can be made by conventional processing techniques, which include a step of drilling signal vias through the carrier from the top surface to intersect various signal planes, power vias through the carrier from the top surface to intersect various power planes, and reference (ground) vias through the carrier from the top surface to intersect various reference planes. The drilled vias are filled with a conducting material, such as plated copper, and the necessary wiring geometry is provided on the surface of the board by conventional photolithographic or silk screening techniques. The chip is then connected either directly or through a ceramic or other dielectric interposer to the surface of the board by means such as solder ball connections. Alternatively to standard plated through hole techniques, parallel processing utilizing layer-to-layer joining techniques can be employed to build the board structure.
The CIC planes are of relatively thin cross-section, i.e., of the order of magnitude of 1 mil. The 1 mil thick CIC can be drilled, with appropriate engineering practices, and hence it is commercially feasible to use the CIC both as a structural member as well as a power or ground plane, since the conductivity and structural properties such as CTE are well combined in the CIC structure.
A typical structure formed of laminae of copper, CIC, and the silica-filled PTFE has a composite coefficient of thermal expansion of about 7-10 ppm/C. This compares to about 6-8 ppm/C for ceramics which are frequently used to mount silicon chips, and also compares to 2-3 ppm/C for silicon chips, thus giving a coefficient of thermal expansion of the copper, CIC and silica-filled PTFE laminate which is relatively well matched to the CTEs of both ceramic and silicon. The difference in CTE between hierarchical structures in an electronic packaging assembly is one key factor determining the stress at the interface between these attached structures during thermal cycling. A second key factor is Young's Modulus. A lower modulus (higher compliancy) reduces stress at the interface. Silica-filled PTFE is particularly well suited to hierarchical packaging assemblies due to its relatively low modulus (approx. 150 kpsi).
In order to provide sufficient power and ground to the integrated circuit chip, it is at times necessary to provide a supplemental power/ground structure, having heavy copper planes and vias, connected electrically and mechanically to the board or card on which the chip or chip carrier is attached. It is further necessary that the stress induced at the interface between this supplemental power/ground assembly and the adjacent circuit card or board which is mounted on it be controlled at sufficiently low levels through thermal cycling such that strain-induced malfunctions do not occur. The use of a power/ground structure having CIC or Invar layers laminated alternately with copper in PTFE or other insulator materials could be engineered or tailored to have a similar CTE as the circuit card or board, which in turn have been engineered to be well matched in CTE to each other and to the chip. However, this would typically require relatively thick CIC or Invar layers in the power/ground assembly, in order to compensate for the thick copper power and ground plane layers with relatively high CTE (17 ppm/C). Layers of CIC this thick are extremely difficult to drill and hence not commercially satisfactory for forming such a power/ground structure. Thus, there exists a need for a power/ground structure having a CTE closely matched to that of the card or board and which can be readily manufactured to provide the necessary power/ground distribution and interconnections while minimizing failures due to thermal cycling.